1. Field of the Invention
The present invention is directed to a spectrum synthesizer for use in testing a pulsed doppler radar and, more particularly, to a system which will generate multiple targets with amplitude and acceleration changes along with specific target profiles for both analog and digital radar inputs.
2. Description of the Related Art
When testing a pulsed doppler radar system, it is necessary to simulate dynamic doppler shifts in the radar's transmission frequency corresponding to the simulated target's velocity. The doppler shift fd is determined by the following equation: EQU fd=((2*v*ft)/c)*cos a (1)
where v is the relative velocity of the target, ft is the radar transmission frequency, c is the speed of light and a is the relative angle between the radar platform velocity vector and the target velocity vector. Equation (1) describes the frequency of the sinusoidal doppler superimposed on the radar's received information.
Conventional target simulators generate the doppler shift by using a sinusoidal lookup table 14 to produce a digital representation of the amplitude of the doppler shifted signal and a digital-to-analog converter 16 to convert the digital value into an analog radar signal as illustrated in FIG. 1. During operation an accumulator 10 accumulates the desired phase of the frequency at a rate fs where the outputs of the accumulator represent the on going phase value or angle of the signal being simulated. That is, the register 12 contains a value (an increment) which represents how much the phase of the signal will change within a period equal to 1/fs. The accumulator 10 sums the phase increments. The phase value is applied to a sinusoidal lookup table, conventionally a read only memory (ROM) storing signal values for each phase value with the phase value acting as the address of the signal value in the ROM. As a result, when the phase value is applied as an address to the ROM, the ROM produces a digital sample of the amplitude of the signal being simulated. This digital amplitude sample is applied to the digital-to-analog converter 16 which produces the corresponding analog signal. As the sine lookup table 14 is addressed by different phase values the digital-to-analog converter 16 produces a stepped or discrete version of the signal being simulated (see FIG. 3a). A low pass filter 18 then smooths this signal producing an analog output suitable for input to the radar being tested.
FIG. 2a illustrates the ideal frequency spectrum at the output of the converter 16 where the desired output is a frequency spike 20 at the desired frequency fo. However, sampling components 22 and 24 are present in the actual output of the converter 16 due to the zero order holding nature of the converter 16. As previously mentioned these components are suppressed by the low pass smoothing filter 18 which has a transfer function 26 as illustrated in FIG. 2b. The final spectrum output by the low pass filter 18 as illustrated in FIG. 2c includes suppressed sampling components that are generally not detectable by the radar.
As mentioned above, as the lookup table 14 is addressed by new values the digital-to-analog converter 16 produces a stepped representation of the simulated signal as illustrated in FIG. 3a. If the desired frequency is doubled then every other location of the lookup table 14 is accessed at twice the original access frequency, thereby doubling the frequency and increasing the size of the steps between each output as shown in FIG. 3b. By using this method the prior art systems are capable of producing smooth frequency changes with no phase discontinuity because the frequency word update is accumulated with the previous sine table lookup value. These conventional systems have been modified to include the capability of frequency shift keying, phase shift keying and on/off keying as typified by U.S. Pat. No. 4,134,072. To provide for operation at today's operating frequencies and to provide an accuracy of at least 16 bits which is necessary to simulate signals at the resolution of today's doppler radars, a 24 bit addressable ROM lookup table is necessary requiring at least one megabyte of addressable storage. This read only memory must also be a high speed memory capable of being addressed at speeds of typically 100 nanoseconds for 3 megahertz bandwidth synthesizers. Such memories are very expensive.